The present invention relates generally to peripheral circuitry for a programmable resistance memory array. More specifically, the present invention is related to driver circuitry for a programmable resistance memory array.
Programmable resistance memory elements formed from materials that can be programmed to exhibit at least a high or low stable resistance state are known in the art. Such programmable resistance elements may be programmed to a high resistance state to store, for example, a logic ZERO data bit. As well, they may be programmed to a low resistance state to store, for example, a logic ONE data bit. Programming a programmable resistance memory element to its high and low resistance states is typically referred to as RESET and SET programming operations, respectively.
One type of material that can be used as the memory material for programmable resistance elements is phase change material. Phase change materials may be programmed between a first structural state where the material is generally more amorphous (less ordered) and a second structural state where the material is generally more crystalline (more ordered). The term xe2x80x9camorphousxe2x80x9d, as used herein, refers to a condition which is relatively structurally less ordered or more disordered than a single crystal and has a detectable characteristic, such as high electrical resistivity. The term xe2x80x9ccrystallinexe2x80x9d, as used herein, refers to a condition which is relatively structurally more ordered than amorphous and has lower electrical resistivity than the amorphous state.
The concept of utilizing electrically programmable phase change materials for electronic memory applications is disclosed, for example, in U.S. Pat. Nos. 3,271,591 and 3,530,441, the contents of which are incorporated herein by reference. The early phase change materials described in the ""591 and ""441 Patents were based on changes in local structural order. The changes in structural order were typically accompanied by atomic migration of certain species within the material. Such atomic migration between the amorphous and crystalline states made programming energies relatively high.
The electrical energy required to produce a detectable change in resistance in these materials was typically in the range of about a microjoule. This amount of energy must be delivered to each of the memory elements in the solid state matrix of rows and columns of memory cells. Such high energy requirements translate into high current carrying requirements for the address lines and for the cell isolation/address device associated with each discrete memory element.
The high energy requirements for programming the memory cells described in the ""591 and ""441 patents limited the use of these cells as a direct and universal replacement for present computer memory applications, such as tape, floppy disks, magnetic or optical hard disk drives, solid state disk flash, DRAM, SRAM, and socket flash memory. In particular, low programming energy is important when the EEPROMs are used for large-scale archival storage. Used in this manner, the EEPROMs would replace the mechanical hard drives (such as magnetic or optical hard drives) of present computer systems. One of the main reasons for this replacement of conventional mechanical hard drives with EEPROM xe2x80x9chard drivesxe2x80x9d would be to reduce the power consumption of the mechanical systems. In the-case of lap-top computers, this is of particular interest because the mechanical hard disk drive is one of the largest power consumers therein. Therefore, it would be advantageous to reduce this power load, thereby substantially increasing the operating time of the computer per charge of the power cells. However, if the EEPROM replacement for hard drives has high programming energy requirements (and high power requirements), the power savings may be inconsequential or at best unsubstantial. Therefore, any EEPROM which is to be considered a universal memory requires low programming energy.
The programming energy requirements of a programmable resistance memory element may be reduced in different ways. For example, the programming energies may be reduced by the appropriate selection of the composition of the memory material. An example of a phase change material having reduced energy requirements is described in U.S. Pat. No. 5,166,758, the disclosure of which is incorporated by reference herein. Other examples of memory materials are provided in U.S. Pat. Nos. 5,296,716, 5,414,271, 5,359,205, and 5,534,712, the disclosures of which are all hereby incorporated by reference herein.
The programming energy requirement may also be reduced through the appropriate modification of the electrical contacts used to deliver the programming energy to the memory material. For example, reduction in programming energy may be achieved by modifying the composition and/or shape and/or configuration (positioning relative to the memory material) of the electrical contacts. Examples of such xe2x80x9ccontact modificationxe2x80x9d are provided in U.S. Pat. Nos. 5,341,328, 5,406,509, 5,534,711, 5,536,947, 5,687,112, 5,933,365, the disclosures of which are all hereby incorporated by reference herein. Examples are also provided in U.S. patent application Ser. Nos. 09/276,273, 09/620,318, 09/677,957 and 09/891,157, the disclosures of which are all hereby incorporated by reference herein. An example of circuitry for reading the state of a programmable resistance memory element is provided in U.S. Pat. No. 6,314,014, the disclosure of which is hereby incorporated by reference herein.
It is possible that currents necessary for appropriately operating a programmable resistance memory element may exceed the currents that can be provided to the memory cell at a given power supply voltage Vcc. For example, programmable resistance memory elements may need to be xe2x80x9cformedxe2x80x9d before achieving normal operating range for a 1 and 0. Forming may require currents which are possibly as much as two to three times that required to either RESET or SET the programmable resistance element. In addition, it is possible that the currents necessary to write to a programmable resistance memory element (such as the current needed to RESET the memory device) may also exceed the current that can be delivered to the memory chip at a given power supply voltage Vcc. (As an example, it is possible that a RESET operation may require as much as about 1.5 ma to about 3 ma while forming may be require currents which are about two or three times this amount or possibly more).
This suggests a need for a higher on-chip voltage to provide the currents necessary for programming and/or forming the programmable resistance memory elements. If the power supply voltage Vcc to the memory chip is increased to provide the necessary currents, then transistors on the memory chip, such as the transistors on the driver circuitry, may need to be designed to accommodate this higher voltage. This may increase the size and cost of the chip. Therefore, there is a need for driver circuitry, which may use conventional transistors, which will permit a column line or a row line of the memory array to be driven to a voltage above the power supply voltage Vcc.
One aspect of the invention is a memory system, comprising: a programmable resistance memory cell coupled to a column line and a row line; and a driver circuit having an output node for outputting an output voltage to the column line and/or the row line, the driver circuit comprising: a plurality of PMOS transistors coupled in series between said output node and a first node of said driver circuit, a plurality of NMOS transistors coupled is series between said output node and a second node of said driver circuit.
Another aspect of the invention is a memory system, comprising: a programmable resistance memory cell coupled to a column line and a row line; and a driver circuit having an output node for outputting an output voltage to the column line and/or the row line, the driver circuit comprising: a plurality of PMOS transistors coupled in series, a plurality of NMOS transistors coupled is series, said plurality of PMOS transistors being coupled in series with said plurality of NMOS at said output node.
Another aspect of the invention is a memory system, comprising: a programmable resistance memory cell coupled to a column line and a row line; and a driver circuit having at least one MOS transistor, said driver circuit outputting an output voltage from an output node to the column line and/or the row line, the driver circuit having a first node supplied with a first voltage and a second node supplied with a second voltage, the magnitude of said first voltage being greater than the magnitude of said second voltage, said driver circuit adapted so that said output voltage is capable of having a magnitude greater than the magnitude of said second voltage, said driver circuit further adapted so that voltages across a drain and a source of said MOS transistor, a gate and the drain of said MOS transistor, and the gate and the source of said MOS transistors have magnitudes that are less than or equal to the magnitude of said second voltage.
Another aspect of the invention is a driver circuit, comprising: at least one MOS transistor, said driver circuit outputting an output voltage from an output node, the driver circuit having a first node supplied with a first voltage and a second node supplied with a second voltage, the magnitude of said first voltage being greater than the magnitude of said second voltage, said driver circuit adapted so that said output voltage is capable of having a magnitude greater than the magnitude of said second voltage, said driver circuit further adapted so that voltages across a drain and a source of said MOS transistor, a gate and the drain of said MOS transistor, and the gate and the source of said MOS transistors have magnitudes that are less than or equal to the magnitude of said second voltage.